共 50 条
- [1] A system-level simulation environment for system-on-chip design 13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2000, : 58 - 62
- [2] System-level simulation environment for system-on-chip design Proc Annu IEEE Int ASIC Conf Exhib, (58-62):
- [3] HW/SW Co-design for Reconfigurable Ultrasonic System-on-Chip Platform 2013 IEEE INTERNATIONAL CONFERENCE ON ELECTRO-INFORMATION TECHNOLOGY (EIT 2013), 2013,
- [4] Energy evaluation methodology for platform based system-on-chip design VLSI 2004: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS, 2004, : 61 - 68
- [5] Application of a system-level HW/SW co-design methodology to an industrial embedded system 2024 13TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING, MECO 2024, 2024, : 64 - 70
- [7] System-Level Behavior Construction and Design Risk Evaluation Based on United Model for System-on-Chip 2009 INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY AND COMPUTER SCIENCE, VOL 1, PROCEEDINGS, 2009, : 382 - +
- [8] Chip-package-board co-design for Complex System-on-Chip (SoC) 2010 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGE & SYSTEMS SYMPOSIUM, 2010,
- [9] Early Stage Chip/Package/Board Co-design Techniques for System-on-Chip 2011 IEEE 20TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS), 2011, : 21 - 24
- [10] A new HW/SW co-design methodology to generate a system level platform based on LISA 2005 6th International Conference on ASIC Proceedings, Books 1 and 2, 2005, : 215 - 218