Channel Noise Scan for Post-layout Check of Printed Circuit Board

被引：0

作者：

Hsu, Jimmy ^{[1
]}

Su, Thonas ^{[1
]}

Ouyang, Gong ^{[2
]}

Chang, Patt ^{[1
]}

Xiao, Kai ^{[2
]}

Lee, Falconee ^{[1
]}

Li, Y. L. ^{[1
]}

机构：

[1] Intel Microelect Asia Ltd, DCG, B1,205 Tun Hwa North Rd, Taipei, Taiwan

[2] Intel Corp, DCG, Dupont, WA 98327 USA

来源：

2015 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC) | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Channel noise scan (CNS) approach is proposed in this paper to efficiently analyse the potential VR-signal coupling issue in the post-layout printed circuit board (PCB) check and the post-silicon debugging of the platform development. CNS is based on a new simulation methodology that includes the whole PCB with signals, voltage regulator (VR) networks, and the interaction. A frequency domain indicator is proposed to systematically analyse the VR-signal coupling problems. This methodology can also provide the ability for the designer to do performance/cost trade-off, layout optimization.

引用

页码：547 / 550

页数：4

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