Low complexity equivalent circuit models for VLSI interconnects

被引：5

作者：

Telescu, M. ^{[1
]}

Tanguy, N. ^{[1
]}

Brehonnet, P. ^{[1
]}

Vilbe, P. ^{[1
]}

Calvez, L. C. ^{[1
]}

机构：

[1] CNRS, LEST, UMR 6165, CS 93837, F-29238 Brest 3, France

来源：

10TH IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/SPI.2006.289242

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we present a technique for generating low complexity equivalent circuit models for VLSI circuit interconnects via the Laguerre-Gram model order reduction (MOR) method developed by our team. We discuss model passivity and equivalent circuit implementation and then show the advantages of our method in preserving important signal parameters such as rise time, delay and overshoot.

引用

页码：271 / +

页数：3

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