Silicon single-electron memory structure

被引：17

作者：

Stone, NJ ^{[1
]}

Ahmed, H ^{[1
]}

机构：

[1] Univ Cambridge, Cavendish Lab, Microelect Res Ctr, Cambridge CB3 0HE, England

来源：

MICROELECTRONIC ENGINEERING | 1998年 / 42卷

关键词：

D O I：

10.1016/S0167-9317(98)00119-1

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A silicon single-electron memory showing clear hysteresis at 4.2K is demonstrated. The memory structure consists of three integrated silicon nanowires. The capability of the memory to read, write and erase electrons from the storage node is shown. The CMOS-compatible fabrication process allows for future integration of these devices with CMOS technology.

引用

页码：511 / 514

页数：4

共 5 条

[1] A silicon single-electron transistor memory operating at room temperature [J].

Guo, LJ ;

Leobandung, E ;

Chou, SY .

SCIENCE, 1997, 275 (5300) :649-651

[2] SINGLE-ELECTRON MEMORY [J].

NAKAZATO, K ;

BLAIKIE, RJ ;

AHMED, H .

JOURNAL OF APPLIED PHYSICS, 1994, 75 (10) :5123-5134

[3] Gate controlled Coulomb blockade effects in the conduction of a silicon quantum wire [J].

Smith, RA ;

Ahmed, H .

JOURNAL OF APPLIED PHYSICS, 1997, 81 (06) :2699-2703

[4]

Tiwari S, 1996, APPL PHYS LETT, V68, P1377, DOI 10.1063/1.116085

[5]

YANO K, 1993, IEDM

← 1 →