A standard cell hardware implementation for finite-difference time domain (FDTD) calculation

Several inherent characteristics make the Finite-Difference Time Domain (FDTD) algorithm almost ideal for the analysis of a wide class of microwave and high-frequency circuits as testified by the great number of papers appeared in the last two decades and by the presence of many software packages on the present market. The application of the FDTD method to practical, three-dimensional problems, however, is often limited by the demand of very large computational resources. In this paper, the architecture of a digital system, dedicated to the solution of the 3D FDTD algorithm and based on a custom VLSI chip, which implements the "field-update" engine, is described. The system is conceived as a PCB module communicating with a host personal computer via a PCI bus and accommodating dedicated synchronous DRAM banks as well. Expectations are that significant speed-up, with respect to state-of-the-art software implementations of the FDTD algorithm, can be achieved.