A low-voltage CMOS LNA with multiple magnetic feedback WLAN applications

A CMOS Low-Noise-Amplifier (LNA) topology that utilizes multiple monolithic transformer magnetic feedback is presented. The proposed topology permits negative and positive feedback to be applied constructively, in order to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance. It also allows for a stable design with adequate gain and large reverse isolation without Noise Figure (NF) degradation. Simulation results indicate voltage conversion gain of 17 dB, NF of 1.6 dB and third-order input intercept point (IIP3) of 13 dBm. The design is being implemented in a 0.13 mu m CMOS technology.