A 4.1-ns compact 54 x 54-b multiplier utilizing sign-select booth encoders

A 54 x 54-b multiplier with only 60 K transistors has been fabricated by 0.25-mu m CMOS technology, To reduce the total transistor count, we have developed two new approaches: sign-select Booth encoding and 48-transistor 4-2 compressor circuits both implemented with pass transistor logic, The sign-select Booth algorithm simplifies the Booth selector circuit and enables us to reduce the transistor count by 45% as compared with that of the conventional one, The new compressor reduces the count by 20% without speed degradation. By using these new circuits, the total transistor count of the multiplier is reduced by 24%, The active size of the 54 x 54-b multiplier is 1.04 x 1.27 mm and the multiplication time is 4.1 ns at a 2.5-V power supply.