TOWARDS A UNIQUE FPGA-BASED IDENTIFICATION CIRCUIT USING PROCESS VARIATIONS

被引：25

作者：

Yu, H. ^{[1
]}

Leong, P. H. W. ^{[1
]}

Hinkelmann, H. ^{[2
]}

Moller, L. ^{[2
]}

Glesner, M. ^{[2
]}

Zipf, P. ^{[3
]}

机构：

[1] Chinese Univ Hong Kong, Dept Comp Sci & Engn, Hong Kong, Hong Kong, Peoples R China

[2] Tech Univ Darmstadt, Inst Microelect Syst, Darmstadt, Germany

[3] Univ Kassel, Digital Technol Lab, Kassel, Germany

来源：

FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS | 2009年

关键词：

D O I：

10.1109/FPL.2009.5272255

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

A compact chip identification (ID) circuit with improved reliability is presented. Ring oscillators are used to measure the spatial process variation and the ID is based on their relative speeds. A novel averaging and postprocessing scheme is employed to accurately determine the faster of two similar-frequency ring oscillators in the presence of noise. Using this scheme, the average number of unstable bits i.e. bits which can change in value between readings, measured on an FPGA is shown to be reduced from 5.3% to 0.9% at 20 degrees C. Within the range 20 - 60 degrees C, the percentage of unstable bits is within 2.8%. An analysis of the effectiveness of the scheme and the distribution of the errors is given over different temperature ranges and FPGA chips.

引用

页码：397 / +

页数：2

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