Energy-efficient code generation for DSP56000 family

被引：0

作者：

Udayanarayanan, S ^{[1
]}

Chakrabarti, C ^{[1
]}

机构：

[1] Arizona State Univ, Dept Elect Engn, Ctr Low Power Elect, Tempe, AZ 85287 USA

来源：

ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2000年

关键词：

code generation; low power;

D O I：

10.1109/LPE.2000.876796

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a procedure to generate energy-efficient code for the Motorola DSP56K processor based on increasing the packing efficiency and minimizing the number of address instructions. The key features are a novel scheduling algorithm that reduces the dependencies between instructions, a register allocation algorithm that spills variables based on their packability, and an address code generation algorithm that minimizes the number of additional instructions. The size of the code generated by this procedure is on the average 45% (25%) smaller than that generated by Motorola's g56K (SPAM).

引用

页码：247 / 249

页数：3