Exploiting concurrency in system-on-chip verification

被引：0

作者：

Xu, Justin ^{[1
]}

Lim, Cheng-Chew ^{[1
]}

机构：

[1] Univ Adelaide, Adelaide, SA 5000, Australia

来源：

2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS | 2006年

基金：

澳大利亚研究理事会;

关键词：

test generation; system-on-chip; verification;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

System-on-chip (SoC) design paradigm makes design verification a more time-consuming task. Therefore, for simulation-based methods, test quality is extremely important. This paper presents a method that increases the test quality by exploiting the concurrency in a system. The main idea is to generalize the elements of concurrency as transfers and then transform the system into a transfer-resource-graph. The graph can be traversed to produce high-quality tests. To further optimize the test quality in terms of concurrency, we are able to generate event-driven test-programs. This is made possible by modelling transfers as active building blocks.

引用

页码：836 / +

页数：2