Mass-productive high performance 0.5μm embedded FRAM technology with triple layer metal

被引：11

作者：

Itoh, A ^{[1
]}

Hikosaka, Y ^{[1
]}

Saito, T ^{[1
]}

Naganuma, H ^{[1
]}

Miyazawa, H ^{[1
]}

Ozaki, Y ^{[1
]}

Kato, Y ^{[1
]}

Mihara, S ^{[1
]}

Iwamoto, H ^{[1
]}

Mochizuki, S ^{[1
]}

Nakamura, M ^{[1
]}

Yamazaki, T ^{[1
]}

机构：

[1] Fujitsu Ltd, Kanegasaki 0294593, Japan

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852757

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Mass-productive 0.5 mu m embedded FRAM(R) with triple layer metal (one local interconnect and two Aluminum interconnects) has been developed. Fabrication processes are fully compatible with high-end logic LSIs using W-CVD via filling process. Using the high performance PZT capacitor and optimized metallization processes, we achieved high retention reliability even after triple layer metal process.

引用

页码：32 / 33

页数：2

共 3 条

[1] LEE SY, 1998, VLSI TECH DIG, P141
[2] PREPARATION OF PB(ZR,TI)O-3 THIN-FILMS ON ELECTRODES INCLUDING IRO2
NAKAMURA, T
NAKAO, Y
KAMISAWA, A
TAKASU, H
[J]. APPLIED PHYSICS LETTERS, 1994, 65 (12) : 1522 - 1524
[3] Advanced 0.5μm FRAM device technology with full compatibility of half-micron CMOS logic device
Yamazaki, T
Inoue, K
Miyazawa, H
Nakamura, M
Sashida, N
Satomi, R
Kerry, A
Katoh, Y
Noshiro, H
Takai, K
Shinohara, R
Ohno, C
Nakajima, T
Furumura, Y
Kawamura, S
[J]. INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, : 613 - 616

← 1 →