Bit-serial interleaved high speed division

被引：7

作者：

Marnane, WP ^{[1
]}

Bellis, SJ

Larsson-Edefors, P

机构：

[1] Univ Coll Cork, Dept Elect Engn & Microelect, Cork, Ireland

[2] Univ Coll Cork, Natl Microelect Res Ctr, Cork, Ireland

[3] Linkoping Univ, Dept Phys, S-58183 Linkoping, Sweden

来源：

ELECTRONICS LETTERS | 1997年 / 33卷 / 13期

关键词：

VLSI; dividing circuits;

D O I：

10.1049/el:19970758

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A bit-serial/word-parallel divider circuit with simplified control requirements, is presented. The circuit uses the non-restoring division algorithm which places a restriction on the speed of the circuit. By introducing the concept of bit interleaving, a high speed design can he implemented of the same circuit complexity as an equivalent size multiplier.

引用

页码：1124 / 1125

页数：2

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