Low Thermal Budget Monolithic Integration of Evanescent-Coupled Ge-on-SOI Photodetector on Si CMOS Platform

被引:52
作者
Ang, Kah-Wee [1 ]
Liow, Tsung-Yang [1 ]
Yu, Ming-Bin [1 ]
Fang, Qing [1 ]
Song, Junfeng [1 ]
Lo, Guo-Qiang [1 ]
Kwong, Dim-Lee [1 ,2 ,3 ]
机构
[1] ASTAR, Inst Microelect, Singapore 117685, Singapore
[2] Natl Univ Singapore, Singapore 119260, Singapore
[3] Republ Polytechn, Singapore 738984, Singapore
关键词
CMOS circuit; germanium; integrated photonics; near infrared; photodetector; silicon-on-insulator (SOI); HIGH-PERFORMANCE;
D O I
10.1109/JSTQE.2009.2025142
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The design and fabrication of a monolithically integrated evanescent-coupled Ge-on-silicon-on-insulator (SOI) photodetector and CMOS circuits were realized on common SOI platform using an "electronic-first and photonic-last" integration approach. High-performance detector with an integrated Si waveguide was demonstrated on epitaxial Ge-absorbing layer selectively grown on an ultrathin SOI substrate. Performance metrics of photodetector designs featuring vertical and lateral PIN configurations were investigated. When operated at a bias of -1.0 V, a vertical PIN detector achieved a lower I-dark of similar to 0.57 mu A as compared to a lateral PIN detector, a value that is below the typical similar to 1 mu A upper limit acceptable for high-speed-receiver design. Very high responsivity of similar to 0.92 A/W was obtained in both detector designs for a wavelength of 1550 nm, which corresponds to a quantum efficiency of similar to 73%. Impulse response measurements showed that the vertical PIN detector gives rise to a smaller full-width at half-maximum of similar to 24.4 ps over a lateral PIN detector, which corresponds to a -3 dB bandwidth of similar to 11.3 GHz. RC time delay is shown to be the dominant factor limiting the speed performance. Eye patterns (pseudorandom binary sequence 2(7)-1) measurement further confirms the achievement of high-speed and low-noise photodetection at a bit rate of 8.5 Gb/s. Excellent transfer and output characteristics have also been achieved by the integrated CMOS inverter circuits in addition to the well-behaved logic functions. The introduction of an additional thermal budget (800 degrees C) arising from the Ge epitaxy growth has no observable detrimental impact on the short-channel control of the CMOS inverter circuit. In addition, we describe the issues associated with monolithic integration and discuss the potential of Ge-detector/Si CMOS receiver for future optical communication applications.
引用
收藏
页码:106 / 113
页数:8
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