A 5.2-GHz CMOS receiver with 62-dB image rejection

被引：7

作者：

Razavi, B ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90024 USA

来源：

2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIC.2000.852844

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 5.2-GHz CMOS receiver employs a double downconversion heterodyne architecture with a local oscillator frequency of 2.6 GHz and applies offset cancellation to the baseband amplifiers. Placing the image around the zero frequency, the receiver achieves an image rejection of 62 dB with no external components while minimizing the flicker noise upconversion in the first mixing operation. Realized in a 0.25-mu m digital CMOS technology, the circuit exhibits a noise figure of 6.4 dB, an IP3 of -15 dBm, and a voltage conversion gain of 43 dB while draining 24 mW from a 2.5-V supply.

引用

页码：34 / 37

页数：4