Pareto-front computation and automatic sizing of CPPLLs

被引：0

作者：

Zou, Jun ^{[1
]}

Mueller, Daniel ^{[1
]}

Graeb, Helmut ^{[1
]}

Schlichtmann, Ulf ^{[1
]}

机构：

[1] Tech Univ Munich, Inst Elect Design Automat, Arcisstr 21, D-80333 Munich, Germany

来源：

ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A comprehensive performance space exploration on system level offers designers a fast way to get insight into the capability of the whole system for a given technology. We consider a charge-pump phase-locked loop (CPPLL) system. In this paper performance space exploration is applied not only to the building blocks but to the whole CPPLL system as well. The trade-offs in the performance of building blocks, e.g. gain jitter and power in VCO, and the performance at system level, e.g. bandwidth, locking time and jitter, will be represented as Pareto-optimal fronts. A hierarchical optimization method is applied to a CPPLL. The sizing process satisfies different application requirements in a flexible manner and can be accomplished in some hours. Experimental results show the efficacy and efficiency of the presented method.

引用

页码：481 / +

页数：2