Two-Dimensional Mapping of Interface Thermal Resistance by Transient Thermal Measurement

被引:17
作者
Gao, Shan [1 ,2 ]
Ngo, Khai D. T. [2 ,3 ]
Lu, Guo-Quan [1 ,4 ]
机构
[1] Virginia Polytech Inst & State Univ, Dept Mat Sci & Engn, Blacksburg, VA 24061 USA
[2] Virginia Polytech Inst & State Univ, Ctr Power Elect Syst, Blacksburg, VA 24061 USA
[3] Virginia Polytech Inst & State Univ, Bradley Dept Elect & Comp Engn, Blacksburg, VA 24061 USA
[4] Virginia Polytech Inst & State Univ, Bradley Dept Elect & Comp Engn, Ctr Power Elect Syst, Blacksburg, VA 24061 USA
关键词
Probes; Thermal resistance; Thermal analysis; Heating systems; Substrates; Temperature measurement; Movable thermal probe; structure function; thermal resistance; transient thermal measurement; two-dimensional (2-D) mapping;
D O I
10.1109/TIE.2020.2984997
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Bonded interfaces in power converters add thermal resistances to heat dissipation. Under cyclic power, temperature, or chemical loading, these interfaces degrade, raising the thermal resistances. Reliability of the thermal interfaces is especially problematic when the bonded area is large because the larger the area the more likely it is to have preexisting defects from processing. To help qualifying the development of a bonding process and quantifying the interface reliability, it would be desirable to have a simple, reliable, and nondestructive measurement technique to obtain a 2-D map of the interface thermal resistance across a large bonded area. Based on the transient thermal method of JEDEC standard 51-14, in this article, we develop a measurement technique that involves moving a thermal probe discretely across a large-area bonded substrate and acquiring the thermal interface resistance under the probe at each location. The probe is made by custom-packaging an insulated-gate bipolar transistor (IGBT) power device. An analytical thermal model is developed to gain insights into the effects of probe materials and structural parameters on the sensitivity of the measurement technique. To obtain a 2-D thermal resistance map of a bonded substrate, the probe is thermally coupled to the substrate at one location through a thermal pad or grease; the device is powered up to a steady-state junction temperature; the power is cutoff; and then the junction temperature during cool-down is recorded. The recorded temperature data are analyzed to derive a thermal structure function of the multilayer material stack. The process is repeated at other locations until a 2-D map of the interface thermal resistance across the entire substrate is completed. This technique is demonstrated on copper-copper bonded samples using either a thermal grease or sintered silver. The resolution of the 2-D mapping technique is evaluated by a copper-grease-copper stack with defects implanted at the bond line.
引用
收藏
页码:4448 / 4456
页数:9
相关论文
共 20 条
[1]  
[Anonymous], 2013, E146113 ASTM
[2]  
[Anonymous], JESD51 J E E C 14 ST
[3]  
[Anonymous], 2004, C17719 ASTM
[4]   Temperature Measurement of Power Semiconductor Devices by Thermo-Sensitive Electrical Parameters-A Review [J].
Avenas, Yvan ;
Dupont, Laurent ;
Khatir, Zoubir .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2012, 27 (06) :3081-3092
[5]   Low-temperature sintered nanoscale silver as a novel semiconductor device-metallized substrate interconnect material [J].
Bai, John G. ;
Zhang, Zhiye Zach ;
Calata, Jesus N. ;
Lu, Guo-Quan .
IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2006, 29 (03) :589-593
[6]   THERMAL-CONDUCTIVITY MEASUREMENT FROM 30-K TO 750-K - THE 3-OMEGA METHOD [J].
CAHILL, DG .
REVIEW OF SCIENTIFIC INSTRUMENTS, 1990, 61 (02) :802-808
[7]   Characterization of Lead-Free Solder and Sintered Nano-Silver Die-Attach Layers Using Thermal Impedance [J].
Cao, Xiao ;
Wang, Tao ;
Ngo, Khai D. T. ;
Lu, Guo-Quan .
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (04) :495-501
[8]   Thermal diffusivity of polymers by the laser flash technique [J].
dos Santos, WN ;
Mummery, P ;
Wallwork, A .
POLYMER TESTING, 2005, 24 (05) :628-634
[9]   Bonding of Large Substrates by Silver Sintering and Characterization of the Interface Thermal Resistance [J].
Gao, Shan ;
Yang, Zhenwen ;
Tan, Yansong ;
Li, Xin ;
Chen, Xu ;
Sun, Zhan ;
Lu, Guo-Quan .
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2019, 55 (02) :1828-1834
[10]   Junction Temperature Extraction Approach With Turn-Off Delay Time for High-Voltage High-Power IGBT Modules [J].
Luo, Haoze ;
Chen, Yuxiang ;
Sun, Pengfei ;
Li, Wuhua ;
He, Xiangning .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2016, 31 (07) :5122-5132