A Highly Linear Neuromorphic Synaptic Device Based on Regulated Charge Trap/Detrap

被引：20

作者：

Choi, Jong-Moon ^{[1
]}

Park, Eun-Je ^{[1
]}

Woo, Je-Joong ^{[1
]}

Kwon, Kee-Won ^{[1
]}

机构：

[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon 16419, South Korea

来源：

IEEE ELECTRON DEVICE LETTERS | 2019年 / 40卷 / 11期

基金：

新加坡国家研究基金会;

关键词：

Linearity; Programming; Tunneling; Capacitance; Erbium; Neuromorphics; Nonvolatile memory; CMOS-compatible; linear programming; charge trap; floating gate; synaptic device; incremental step pulse programming (ISPP);

D O I：

10.1109/LED.2019.2943113

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this letter, we present highly linear potentiation/depression behaviors of a neuromorphic synaptic device made of CMOS-compatible floating gate (FG) cells. The kinetics of the charge trap/detrap mechanism under various pulse shapes are analyzed to design a simple 2C-4T FG cell with a modulated column write driver for embedded incremental step pulse programming (ISPP) via analog feedback. Utilizing real-time ISPP, the linearity and symmetry of the weight update were significantly improved due to the content-aware programming strength. Moreover, the proposed circuit technique provides flexibility regarding the size of the program/erase steps in addition to the superior linearity. The proposed FG cells with peripheral circuits are fabricated using 180nm CMOS technology and exhibited a differential non-linearity (DNL) less than 0.946 least significant bit (LSB) with 100 weight states. The excellent linearity remains unchanged even when the directions of potentiation /depression are reversed throughout the entire range.

引用

页码：1848 / 1851

页数：4

共 15 条

[1] Equivalent-accuracy accelerated neural-network training using analogue memory [J].

Ambrogio, Stefano ;

Narayanan, Pritish ;

Tsai, Hsinyu ;

Shelby, Robert M. ;

Boybat, Irem ;

di Nolfo, Carmelo ;

Sidler, Severin ;

Giordano, Massimo ;

Bodini, Martina ;

Farinha, Nathan C. P. ;

Killeen, Benjamin ;

Cheng, Christina ;

Jaoudi, Yassine ;

Burr, Geoffrey W. .

NATURE, 2018, 558 (7708) :60-+

[2]

[Anonymous], 2018, IEEE INT ELECT DEVIC, DOI DOI 10.1016/J.MICRES.2018.06.008

[3] Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element [J].

Burr, Geoffrey W. ;

Shelby, Robert M. ;

Sidler, Severin ;

di Nolfo, Carmelo ;

Jang, Junwoo ;

Boybat, Irem ;

Shenoy, Rohit S. ;

Narayanan, Pritish ;

Virwani, Kumar ;

Giacometti, Emanuele U. ;

Kuerdi, Bulent N. ;

Hwang, Hyunsang .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (11) :3498-3507

[4]

Chang S. De Ted, 1998, U.S.Patent, Patent No. [5761121A, 5761121]

[5] A Study of Endurance Issues in HfO2-Based Ferroelectric Field Effect Transistors: Charge Trapping and Trap Generation [J].

Gong, Nanbo ;

Ma, Tso-Ping .

IEEE ELECTRON DEVICE LETTERS, 2018, 39 (01) :15-18

[6] Unsupervised Learning Using Charge-Trap Transistors [J].

Gu, Xuefeng ;

Iyer, Subramanian S. .

IEEE ELECTRON DEVICE LETTERS, 2017, 38 (09) :1204-1207

[7]

Jerry Matthew, 2017, 2017 IEEE International Electron Devices Meeting (IEDM), P621, DOI 10.1109/IEDM.2017.8268338

[8] Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High-k-Metal-Gate CMOS Technologies [J].

Khan, Faraz ;

Cartier, Eduard ;

Woo, Jason C. S. ;

Iyer, Subramanian S. .

IEEE ELECTRON DEVICE LETTERS, 2017, 38 (01) :44-47

[9]

Kim M., 2018, IEEE INT ELECT DEVIC

[10] A low power CMOS compatible embedded EEPROM for passive RFID tag [J].

Lee, Kyoung-Su ;

Chun, Jung-Hoon ;

Kwon, Kee-Won .

MICROELECTRONICS JOURNAL, 2010, 41 (10) :662-668

← 1 2 →