Low complexity semi-systolic multiplication architecture over GF(2m)

被引：6
|
作者：
Choi, Se-Hyu [1 ]
Lee, Keon-Jik [1 ]
机构：
[1] Kyungpook Natl Univ, Sch Architectural Civil Environm & Energy Engn, Taegu 702701, South Korea
来源：
IEICE ELECTRONICS EXPRESS | 2014年 / 11卷 / 20期
关键词：
modular multiplication; finite field arithmetic; systolic array; CONCURRENT ERROR-DETECTION; POLYNOMIAL BASIS MULTIPLIER;
D O I：
10.1587/elex.11.20140713
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a semi-systolic Montgomery multiplier based on the redundant basis representation of the finite field elements. The proposed multiplier has less hardware and time complexities compared to related multipliers. We also propose a serial systolic Montgomery multiplier that can be applied well in space-limited hardware. Furthermore, a simple inversion based on the proposed scheme is presented.
引用
收藏
页数：6
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