Emulation of an ASIC Power and Temperature Monitor System for FPGA Prototyping

Monitoring information can be used during system runtime to increase system lifetime and reliability. Examples of such monitoring information are power or temperature values. They provide the system with relevant information about the current hardware health. In a resource-aware computing system, where resources are allocated according to current requirements, the current hardware status must be included in the decisions for resource allocation in order to select the best suitable application-resource pairs and at the same time reach system targets like limiting the system temperature. To test and optimize the system's resource allocation already in the design phase, FPGA prototyping is often required before its implementation in an ASIC. Since the behavior of measured power and temperature evolution in FPGA and ASIC differ, data from power and temperature sensors on both platforms would have significant differences. To efficiently test and optimize the resource allocation for an ASIC implementation, it is necessary to provide the FPGA prototype with modeled power and temperature values characterized from an ASIC implementation. This paper describes how to emulate the behavior of an emulated ASIC power and temperature monitor system (eTP-Mon) on FPGA. The approach for emulating the power monitor is based on an instruction-level energy model. For emulating the temperature monitor, a thermal RC model is used. It is shown that eTPMon can supply an invasive MPSoC with the hardware status information (power and temperature of the cores) needed for efficient resource-aware load distribution to develop a resource-aware computing system concept. As a proof of concept different operating strategies and control targets were evaluated for a 2-tile invasive MPSoC.