Offset Voltage Analysis and Enable Signal Rise Time Control Based Offset Reduction Technique of Current-Latched Sense Amplifier

被引：3
|
作者：
Na, Taehui [1 ,2 ]
机构：
[1] Incheon Natl Univ, Dept Elect Engn, Incheon 22012, South Korea
[2] Incheon Natl Univ, Res Inst Engn & Technol, Incheon 22012, South Korea
来源：
2021 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC) | 2021年
基金：
新加坡国家研究基金会;
关键词：
Latch type; offset voltage; sense amplifier;
D O I：
10.1109/ICEIC51217.2021.9369783
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper analyzes input referred offset voltage (VOS) of a current-latched sense amplifier (CLSA) caused by a mismatch of input NMOS pair, latch NMOS pair, latch PMOS pair, and precharge PMOS pair. In addition, SA enable rise time control based VOS reduction technique is proposed. HSPICE simulation results based on industry-compatible 28-nm model parameters show that the proposed technique can reduce VOS caused by latch NMOS pair's mismatch by 33%.
引用
收藏
页数：2
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