Low Parasitic Capacitance and Low-Power CMOS Capacitive Fingerprint Sensor

In this paper, a low parasitic capacitance and low-power CMOS capacitive fingerprint sensor readout circuit is presented. The side effect of parasitic capacitance has been under control with novel layout structure in sensor cell, and minimal size switch is used to reduce non-ideal effects of MOS switch and achieve good linearity. Power dissipation is also reduced with quiescent current control in buffer amplifier of sensor cell. A prototype chip with 32 x 32 array size has been fabricated using TSMC 0.35 mu m CMOS process. The chip works at 3.3V power supply and operates at 4MHz clock rate. Capacitance value from 0ff to 60fF can be sensed, corresponding analog output voltage is from 3.02V to 1.57V and the digital output is 6 bits. The overall power consumption is less than 5.5mW.