Trade-offs in the integration of high performance devices with trench capacitor DRAM

被引：14

作者：

Crowder, S ^{[1
]}

Stiffler, S ^{[1
]}

Parries, P ^{[1
]}

Bronner, G ^{[1
]}

Nesbit, L ^{[1
]}

Wille, W ^{[1
]}

Powell, M ^{[1
]}

Ray, A ^{[1
]}

Chen, B ^{[1
]}

Davari, B ^{[1
]}

机构：

[1] IBM Corp, Semicond Res & Dev Ctr, Hopewell Junction, NY 12533 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.649452

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper demonstrates it is possible to enhance the device performance of a standard DRAM process by 35% with only a moderate reduction in retention time. We have also merged high-performance logic devices and working DRAM at the cost of an appreciable degradation in retention behavior and a slightly larger cell. The device performance is 1.82x the base process. This demonstrates that embedding DRAM in a high-performance technology is feasible although the optimum trade-off between performance, density, retention time, cost and power depends on the application.

引用

页码：45 / 48

页数：4