FPGA Implementations of SHA-3 Candidates: CubeHash, Grostl, LANE, Shabal and Spectral Hash

被引:4
作者
Baldwin, Brian [1 ]
Byrne, Andrew [1 ]
Hamilton, Mark [1 ]
Hanley, Neil [1 ]
McEvoy, Robert P. [1 ]
Pan, Weibo [1 ]
Marnane, William P. [1 ]
机构
[1] Univ Coll Cork, Dept Elect & Elect Engn, Claude Shannon Inst Discrete Math Coding & Crypto, Cork, Ireland
来源
PROCEEDINGS OF THE 2009 12TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, ARCHITECTURES, METHODS AND TOOLS | 2009年
关键词
D O I
10.1109/DSD.2009.162
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Hash functions are widely used in, and form an important part of many cryptographic protocols. Currently, a public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware will form one of the evaluation criteria. In this paper, we focus on five of these candidate algorithms, namely Cube Hash, Grostl, LANE, Shabal and Spectral Hash. Using Xilinx Spartan-3 and Virtex-5 FPGAs, we present architectures for each of these hash functions, and explore area-speed trade-offs in each design. The efficiency of various architectures for the five hash functions is compared in terms of throughput per unit area. To the best of the authors' knowledge, this is the first such comparison of these SHA-3 candidates in the literature.
引用
收藏
页码:783 / 790
页数:8
相关论文
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