Hybrid Millimeter-Wave Massive MIMO Systems with Low CSI Overhead and Few-Bit DACs/ADCs

被引:13
作者
Koc, Asil [1 ]
Le-Ngoc, Tho [1 ]
机构
[1] McGill Univ, Dept Elect & Comp Engn, Montreal, PQ, Canada
来源
2020 IEEE 92ND VEHICULAR TECHNOLOGY CONFERENCE (VTC2020-FALL) | 2020年
基金
加拿大自然科学与工程研究理事会;
关键词
Massive MIMO; millimeter-wave; hybrid pre-coding; hybrid combining; analog-to-digital converter; digital-to-analog; converter; low CSI overhead; AQNM; 5G;
D O I
10.1109/VTC2020-Fall49728.2020.9348805
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Hybrid precoding/combining (HPC) architecture is a promising candidate for millimeter-wave (mmWave) massive multiple-input multiple-output (MIMO) systems. It is capable of reducing the hardware cost/complexity and power consumption compared to the full-digital precoding/combining (FDPC) while keeping the similar spectral efficiency. Most of the prior works on HPC consider the availability of full channel state information (CSI) to design both radio-frequency (RF) and baseband (BB) stages. In this work, an angular-based HPC (AB-HPC) design requiring low CSI overhead is proposed for mmWave massive MIMO systems equipped with low-resolution digital-to-analog converters (DAC) and analog-to-digital converters (ADC). Based on the 3D geometry-based mmWave channel model, the transmit and receive RF beamformers are first developed based on the slow time-varying angle-of-departure (AoD) and angle-of-arrival (AoA) parameters, respectively. Then, the transmit BB precoder and receive BB combiner are designed by employing the reducedsize effective CSI seen from the BB-stages. Considering the effect of low-resolution DACs/ADCs, the receive BB combiner is obtained by the minimum mean square error (MMSE) criterion. The numerical results reveal that the proposed AB-HPC technique can closely approach the achievable rate performance of FDPC while remarkably reducing the number of power-hungry RF chains and CSI overhead size (e.g., around 94:1% 98:5%). Moreover, the quantization error occurred due to the lowresolution DACs/ADCs causes a performance floor. For a given signal-to-noise ratio (SNR), we also ask the required number of bits for the low-resolution DACs/ADCs for converging to the same achievable rate performance in full-precision DACs/ADCs.
引用
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页数:5
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