Current Stress Reduction for DC-Link Capacitors of Three-Phase VSI With Carrier-Based Continuous PWM

被引：11

作者：

Nishizawa, Koroku ^{[1
]}

Itoh, Jun-ichi ^{[2
]}

Odaka, Akihiro ^{[3
]}

Toba, Akio ^{[3
]}

Umida, Hidetoshi ^{[3
]}

Fujita, Satoru ^{[3
]}

机构：

[1] Nagaoka Univ Technol, Dept Sci Technol Innovat, Nagaoka, Niigata 9402188, Japan

[2] Nagaoka Univ Technol, Dept Elect Elect & Informat Engn, Nagaoka, Niigata 9402188, Japan

[3] Fuji Elect Co Ltd, Shinagawa Ku, Tokyo 1410032, Japan

来源：

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS | 2019年 / 55卷 / 06期

关键词：

Continuous pulsewidthmodulation (CPWM); dc-link capacitor; inverter dc-link current harmonics; two-level voltage source inverter (VSI); SENSORLESS CONTROL; SATURATION; MOTORS;

D O I：

10.1109/TIA.2019.2932701

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This article proposes a novel continuous pulsewidth modulation (CPWM) method to reduce dc-link current harmonics in voltage source inverters over wide range of load power factor. This modulation method contributes to a current stress reduction of dc-link smoothing capacitor and a suppression of its temperature rise. Furthermore, high-cost digital hardware, such as a field-programmable gate array, is not necessary because this modulation is implemented with only one carrier. The dc-link current harmonics are reduced by shifting voltage references in every half control period to reduce a fluctuation of the dc-link current around its average value. Experimental results confirm that the application of the proposed CPWM reduces the dc-link current harmonics by 24.2% at most and lowers an equilibrium capacitor temperature by 6.0 degrees C compared to the conventional CPWM.

引用

页码：6061 / 6072

页数：12