Wafer-level high density multifunctional integration (HDMI) for low-cost micro/nano/electro-opto/bio heterogeneous systems

被引：0

作者：

Gutmann, RJ ^{[1
]}

Lu, JQ ^{[1
]}

McMahon, JJ ^{[1
]}

Persans, PD ^{[1
]}

Cale, TS ^{[1
]}

Eisenbraun, ET ^{[1
]}

Castracane, J ^{[1
]}

Kaloyeros, AE ^{[1
]}

机构：

[1] Rensselaer Polytech Inst, Focus Ctr, Troy, NY 12180 USA

来源：

NANOTECH 2003, VOL 1 | 2003年

关键词：

High Density Multifunctional Integration (HDMI); 3D integration; heterogeneous systems; system-on-a-chip (SoC); system-in-a-package (SiP);

D O I：

暂无

中图分类号：

R318 [生物医学工程];

学科分类号：

0831 ;

摘要：

A technology platform demonstrating wafer-level high density multifunctional integration (HDMI) based upon three-dimensional (3D) technology is described, which offers the potential for future low-cost integration of information processing and sensor/actuator technologies. This HDMI scheme alleviates processing and material constraints associated with system-on-a-chip (SoC) electronic integration, while providing the capability of extension to opto-electronic, bio-molecular and other micro/nano heterogeneous system applications. Process development results obtained to date are discussed, and approaches to heterogeneous integration using this novel technology platform are outlined.

引用

页码：530 / 533

页数：4

共 11 条

[1] [Anonymous], 2001, INT TECHNOLOGY ROADM
[2] [Anonymous], INT TECHN 1999 IEEE
[3] Interconnect limits on gigascale integration (GSI) in the 21st century
Davis, JA
Venkatesan, R
Kaloyeros, A
Beylansky, M
Souri, SJ
Banerjee, K
Saraswat, KC
Rahman, A
Reif, R
Meindl, JD
[J]. PROCEEDINGS OF THE IEEE, 2001, 89 (03) : 305 - 324
[4] Three-dimensional (3D) ICs: A technology platform for integrated systems and opportunities for new polymeric adhesives
Gutmann, RJ
Lu, JQ
Kwon, Y
McDonald, JF
Cale, TS
[J]. POLYTRONIC 2001, PROCEEDINGS, 2001, : 173 - 180
[5] GUTMANN RJ, 2002, P 2002 AVS 3 INT C M, P23
[6] KWON Y, 2001, 6 INT S SEM WAF BOND
[7] Three-dimensional shared memory fabricated using wafer stacking technology
Lee, KW
Nakamura, T
Ono, T
Yamada, Y
Mizukusa, T
Hashimoto, H
Park, KT
Kurino, H
Koyanagi, M
[J]. INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 165 - 168
[8] A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects
Lu, JQ
Kwon, Y
Rajagopalan, G
Gupta, M
McMahon, J
Lee, KW
Kraft, RP
McDonald, JF
Cale, TS
Gutmann, RJ
Xu, B
Eisenbraun, E
Castracane, J
Kaloyeros, A
[J]. PROCEEDINGS OF THE IEEE 2002 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2002, : 78 - 80
[9] LU JQ, 2002, AMC 2002
[10] Ramm P, 2001, MAT RES S C, P159

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