Layout-aware Soft Error Rate Estimation Technique for Integrated Circuits under the Environment with Energetic Charged Particles

被引：1

作者：

Balbekov, A. O. ^{[1
]}

Gorbunov, M. S. ^{[1
,2
]}

Bobkov, S. G. ^{[1
,2
]}

机构：

[1] Russian Acad Sci, Sci Res Inst Syst Anal, Fed State Inst, Nakhimovskiy Prospekt St 36b1, Moscow 117218, Russia

[2] Natl Res Nucl Univ MEPhI, Moscow Engn Phys Inst, Kashirskoe Highway 31, Moscow 115409, Russia

来源：

INTERNATIONAL CONFERENCE ON PARTICLE PHYSICS AND ASTROPHYSICS | 2017年 / 798卷

基金：

俄罗斯基础研究基金会;

关键词：

DESIGN;

D O I：

10.1088/1742-6596/798/1/012209

中图分类号：

P1 [天文学];

学科分类号：

0704 ;

摘要：

Single Event Transient (SET) is a current and voltage disturbance in an integrated circuit (IC), caused by charged particle impact. In modern IC technologies single charged particle can cause multiple SETs on multiple electrical nodes, this can lead to faults. There are several mitigation techniques with their drawbacks affecting circuit performance. This work presents a comparison of experimental data with simulation results acquired by the means of our technique and tools. Our technique is able to simulate sub-100 nm IC performance under multiple SET using industry standard SPICE simulator, without incorporation of a T-CAD or physical measurements, and taking into account layout of the device.

引用

页数：5

共 3 条

[1] Layout-aware Simulation of Soft Errors in sub-100 nm Integrated Circuits
Balbekov, A.
Gorbunov, M.
Bobkov, S.
INTERNATIONAL CONFERENCE ON MICRO- AND NANO-ELECTRONICS 2016, 2016, 10224
[2] A Placement-aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology
Paliaroutis, Georgios Ioannis
Tsoumanis, Pelopidas
Evmorfopoulos, Nestor
Dimitriou, George
Stamoulis, Georgios I.
2018 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), 2018,
[3] Scaling analytical models for soft error rate estimation under a multiple-fault environment
Hescott, Christian J.
Ness, Drew C.
Lija, David J.
DSD 2007: 10TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS, 2007, : 641 - +

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