Correlation branch selection for extended tracking range delay-locked loops

被引:4
|
作者
Wilde, A [1 ]
机构
[1] DLR, German Aerosp Ctr, D-82230 Wessling, Germany
来源
EUROPEAN TRANSACTIONS ON TELECOMMUNICATIONS | 1998年 / 9卷 / 01期
关键词
D O I
10.1002/ett.4460090107
中图分类号
TN [电子技术、通信技术];
学科分类号
0809 ;
摘要
In spread spectrum systems the delay-locked loop is commonly used to track the spreading code. A problem is to design the delay-locked loop to be both accurate and robust against disturbances which normally requires a tradeoff. The use of extended tracking range delay-locked loops increases the ability of the system to maintain lock even for large Doppler frequency offsets. The extended tracking range is achieved by using more than two correlators to form the error detector characteristic. However, the noise level in the synchronization loop is increased by every additional correlator leading to larger tracking jitter. In this paper an algorithm is proposed which reduces the noise level in the loop considerably. This is done by selecting only those correlation branches with an useful control signal. The investigated performance criteria are the tracking jitter and the mean time to loose lock. Both analytical and simulation results are presented. The extended tracking range delay-locked loop with correlation branch selection shows very promising performance results for both criteria at medium to high signal-to-noise ratios. It approaches the performance of the classical delay-locked loop for the tracking jitter and has a much larger mean time to loose lock than the classical delay-locked loop.
引用
收藏
页码:57 / 64
页数:8
相关论文
共 50 条
  • [1] Correlation branch selection for extended tracking range delay-locked loops
    German Aerospace Cent , Wessling, Germany
    Eur Trans Telecommun, 1 (57-64):
  • [2] Delay-locked loop with correlation branch selection
    Wilde, A
    GLOBECOM 97 - IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, CONFERENCE RECORD, VOLS 1-3, 1997, : 614 - 618
  • [3] Jitter of Delay-Locked Loops Due to PFD
    Gholami, Mohammad
    Ardeshir, Gholamreza
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (10) : 2176 - 2180
  • [4] Low jitter Butterworth delay-locked loops
    Chang, HH
    Sun, CH
    Liu, SI
    2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, : 177 - 180
  • [5] Steady-state analysis of delay-locked loops tracking binary Markovian sequences
    Nagata, Keisuke
    Fujisaka, Hisato
    Kamio, Takeshi
    Ahn, Chang-Jun
    Haeiwa, Kazuhisa
    IEICE NONLINEAR THEORY AND ITS APPLICATIONS, 2010, 1 (01): : 153 - 165
  • [6] Design-for-testability for embedded delay-locked loops
    Egan, T
    Mourad, S
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (08) : 984 - 988
  • [7] A novel tracking jitter computation method for delay-locked loops in spread-spectrum systems
    Groh, Ingmar
    Gentner, Christian
    Selva, Jesus
    TRANSACTIONS ON EMERGING TELECOMMUNICATIONS TECHNOLOGIES, 2012, 23 (08): : 715 - 727
  • [8] Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces
    Lee, Hyun-Woo
    Kim, Chulwoo
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (04) : 701 - 711
  • [9] Quasi-coherent delay-locked loops for fading channels
    Latvaaho, M
    Vallstrom, J
    IEEE ISSSTA '96 - IEEE FOURTH INTERNATIONAL SYMPOSIUM ON SPREAD SPECTRUM TECHNIQUES & APPLICATIONS, PROCEEDINGS, VOLS 1-3, 1996, : 455 - 459
  • [10] A comprehensive phase-transfer model for delay-locked loops
    Burnham, James R.
    Wei, Gu-Yeon
    Yang, Chih-Kong Ken
    Hindi, Haitham
    PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2007, : 627 - +