Implementation of viterbi decoder for WCDMA system

This paper describes the implementation of soft-decision Viterbi decoder on TMS320C62x DSP. In this work a soft-decision Viterbi decoder is implemented on code rate 113 and constraint length 9. Originally the aim is to achieve a decoding rate of 32Kbps as per WCDMA IS-95 standard recommendation, which also employs a convolutional encoder with 8 trellis states and, Viterbi decoder with 256 states in the trellis. Presently there are numerous standards for digital cellular systems, especially when considering the third generation system. Each of these contains operation modes utilizing convolutional coding which is usually decoded via Viterbi decoder. In each standard there are different formulations of this coding with each form imparting requirements upon the decoder. This gives rise the need for Viterbi decoders with highly flexible capabilities. Realizing such flexibilities in DSP software is straightforward. This paper presents a flexible Viterbi decoder constructed to operate as a loosely coupled coprocessor for the DSP. Single shift register convolutional codes with 1/In code rates are targeted. Some application of the implemented decoder and the bottlenecks in the implementation have also been discussed