Real Time Video Processing on FPGA Using on the Fly Partial Reconfiguration

被引：12

作者：

Bhandari, Sheetal U. ^{[1
]}

Subbaraman, Shaila ^{[2
]}

Pujari, Shashank S. ^{[1
]}

Mahajan, Rashmi ^{[1
]}

机构：

[1] Int Inst Informat Technol, Pune, Maharashtra, India

[2] Walchand Coll Engn, Sangli, India

来源：

PROCEEDINGS OF THE 2009 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING SYSTEMS | 2009年

关键词：

reconfigurable computing; partial reconfiguration; run time reconfiguration;

D O I：

10.1109/ICSPS.2009.32

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The development of Field programmable Gate Arrays (FPGAs) had tremendous improvement in last few years. FPGA based solutions have shown significant speedups compared with software and DSP based approaches for several application domains such as signal and image processing, graph algorithms, genetic algorithms and cryptography among others. Runtime Partial reconfiguration of FPGA is an attractive feature which offers countless benefits across multiple industries. Xilinx has supported partial reconfiguration for many generations of devices. This can be taken advantage of to substitute inactive parts of a hardware systems and adapt the complete chip to a different requirement of an application. This paper describes the implementation of mean and median filters for real time video signal on Virtex-4 FPGA using Partial reconfiguration. The considerable savings in device resources, bit stream size and configuration time is observed and tabulated in this paper.

引用

页码：244 / +

页数：2