SymBIST: Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety

被引:24
作者
Pavlidis, Antonios [1 ]
Louerat, Marie-Minerve [1 ]
Faehn, Eric [2 ]
Kumar, Anand [3 ]
Stratigopoulos, Haralampos-G. [1 ]
机构
[1] Sorbonne Univ, CNRS, LIP6, F-75252 Paris, France
[2] STMicroelectronics, F-38920 Crolles, France
[3] STMicroelectronics, Greater Noida 201308, India
关键词
Built-in self-test; Integrated circuit modeling; Standards; Monitoring; Analog-digital conversion; Windows; Transient analysis; Analog and mixed-signal integrated circuit testing; built-in self-test; design-for-test; defect-oriented test; defect simulation; on-line test; concurrent error detection; BIST; GENERATION; OSCILLATOR; SIMULATION; DESIGN;
D O I
10.1109/TCSI.2021.3067180
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We propose a Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST (SymBIST). SymBIST exploits inherent symmetries in an A/M-S IC to construct signals that are invariant by default, and subsequently checks those signals against a tolerance window. Violation of invariant properties points to the occurrence of a defect or abnormal operation. SymBIST is designed to serve as a functional safety mechanism. It is reusable ranging from post-manufacturing test, where it targets defect detection, to on-line test in the field of operation, where it targets low-latency detection of transient failures and degradation due to aging. We demonstrate SymBIST on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). SymBIST features high defect coverage, short test time, low overhead, zero performance penalty, and has a fully digital interface making it compatible with modern digital test access mechanisms.
引用
收藏
页码:2580 / 2593
页数:14
相关论文
共 42 条
  • [1] [Anonymous], 2011, P DES AUT TEST EUR M
  • [2] Optimizing sinusoidal histogram test for low cost ADC BIST
    Azaïs, F
    Bernard, S
    Bertrand, Y
    Renovell, M
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2001, 17 (3-4): : 255 - 266
  • [3] A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΔΣ ADC
    Barragan, Manuel J.
    Alhakim, Rshdee
    Stratigopoulos, Haralampos-G.
    Dubois, Matthieu
    Mir, Salvador
    Le Gall, Herve
    Bhargava, Neha
    Bal, Ankur
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2016, 63 (11) : 1876 - 1888
  • [4] Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques
    Barragan, Manuel J.
    Stratigopoulos, Haralampos-G.
    Mir, Salvador
    Le-Gall, Herve
    Bhargava, Neha
    Bal, Ankur
    [J]. IEEE DESIGN & TEST, 2016, 33 (06) : 46 - 54
  • [5] Concurrent error detection and fault-tolerance linear analog circuits using continuous checksums
    Chatterjee, Abhijit
    [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993, 1 (02) : 138 - 150
  • [6] Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches
    Chauhan, Hari
    Choi, Yongsuk
    Onabajo, Marvin
    Jung, In-Seok
    Kim, Yong-Bin
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (03) : 497 - 506
  • [7] USER-SMILE: Ultrafast Stimulus Error Removal and Segmented Model Identification of Linearity Errors for ADC Built-in Self-Test
    Chen, Tao
    Jin, Xiankun
    Geiger, Randall L.
    Chen, Degang
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2018, 65 (07) : 2059 - 2069
  • [8] Automatic generation of test infrastructures for analog integrated circuits by controllability and observability co-optimization
    Coyette, Anthony
    Esen, Baris
    Dobbelaere, Wim
    Vanhooren, Ronny
    Gielen, Georges
    [J]. INTEGRATION-THE VLSI JOURNAL, 2016, 55 : 393 - 400
  • [9] Dobbelaere W., 2016, 2016 IEEE INT TEST C, P1, DOI DOI 10.1109/TEST.2016.7805829
  • [10] On-chip analog signal generation for mixed-signal built-in self-test
    Dufort, B
    Roberts, GW
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (03) : 318 - 330