A Fully Integrated 60-GHz 5-Gb/s QPSK Transceiver With T/R Switch in 65-nm CMOS

被引：22

作者：

Kuang, Lixue ^{[1
]}

Yu, Xiaobao ^{[1
]}

Jia, Haikun ^{[1
]}

Chen, Lei ^{[1
]}

Zhu, Wei ^{[1
]}

Wei, Meng ^{[1
]}

Song, Zheng ^{[1
]}

Wang, Zhihua ^{[1
]}

Chi, Baoyong ^{[1
]}

机构：

[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China

来源：

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES | 2014年 / 62卷 / 12期

基金：

中国国家自然科学基金;

关键词：

CMOS; millimeter wave; 60; GHz; transceiver; wideband; SPDT SWITCH; DESIGN;

D O I：

10.1109/TMTT.2014.2364589

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fully integrated 60-GHz 5-Gb/s quadrature phase-shift keying (QPSK) transceiver with the transmit/receive (T/R) switch in 65-nm CMOS is presented. By utilizing the co-design of the T/R switch with the power amplifier (PA)/low-noise amplifier, pi-type wideband passive network technique, as well as the modified distributed-amplifier-based PA, the RF bandwidth of the transmitter (TX)/receiver (RX) is extended to 5 GHz. An inductorless wideband programmable gain amplifier with negative capacitive neutralization, consisting of two modified Cherry-Hooper amplifier stages, provides 18-dB variable gain range with enough bandwidth. Due to the proposed bandwidth extension techniques, the measured double-side link bandwidth of the TX/RX is wider than 5 GHz so that 5-Gb/s QPSK communication could be supported. A direct QPSK modulator and mixed-signal QPSK demodulator are integrated to avoid the high-power high-complexity analog-digital converter/digital- analog converter and high-speed digital baseband processing. Together with the integrated T/R switch, the power consumption and the cost of the transceiver are significantly lowered while achieving up to 5-Gb/s data rate. The local oscillating signals and various clocks are provided by a fully differential phase-locked loop frequency synthesizer with -97.2-dBc/Hz phase noise at 1-MHz offset from a 40-GHz carrier. The measured error vector magnitude of the TX is -21.9 dB, while the bit error rate of the RX with a -52-dBm sine-wave input is below 8e - 7 when transmitting/receiving 5-Gb/s data. The transceiver is powered by 1.0- and 1.2-V supply (except the phase-frequency detector and charge-pump in the frequency synthesizer, which are powered by a 2.5-V supply) and consumes 135 mW in the TX mode and 176 mW in the RX mode, with a chip area of 3 mm x 2 mm.

引用

页码：3131 / 3145

页数：15

共 25 条

[11]

Ma K., 2014, Power Electronics, IEEE Transactions on, VPP,, P1

[12]

Mitomo T., 2012, 2012 IEEE International Solid-State Circuits Conference (ISSCC), P266, DOI 10.1109/ISSCC.2012.6177010

[13]

Okada K, 2014, ISSCC DIG TECH PAP I, V57, P346, DOI 10.1109/ISSCC.2014.6757463

[14]

Redant T, 2014, ISSCC DIG TECH PAP I, V57, P342, DOI 10.1109/ISSCC.2014.6757461

[15] A silicon 60-GHz receiver and transmitter chipset for broadband communications [J].

Reynolds, Scott K. ;

Floyd, Brian A. ;

Pfeiffer, Ullrich R. ;

Beukema, Troy ;

Grzyb, Janusz ;

Haymes, Chuck ;

Gaucher, Brian ;

Soyuer, Mehmet .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (12) :2820-2831

[16]

Saigusa S, 2014, ISSCC DIG TECH PAP I, V57, P348, DOI 10.1109/ISSCC.2014.6757464

[17]

Siligaris A., 2011, 2011 IEEE International Solid-State Circuits Conference (ISSCC 2011), P162, DOI 10.1109/ISSCC.2011.5746264

[18] A 1 Gb/s Mixed-Signal Baseband Analog Front-End for a 60 GHz Wireless Receiver [J].

Sobel, David Amory ;

Brodersen, Robert W. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (04) :1281-1289

[19] A 10 Gb/s 45 mW Adaptive 60 GHz Baseband in 65 nm CMOS [J].

Thakkar, Chintan ;

Kong, Lingkai ;

Jung, Kwangmo ;

Frappe, Antoine ;

Alon, Elad .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (04) :952-968

[20]

Tsukizawa T, 2013, ISSCC DIG TECH PAP I, V56, P230, DOI 10.1109/ISSCC.2013.6487712

← 1 2 3 →