Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

被引：10

作者：

Fenouilet-Beranger, C. ^{[1
,2
]}

Perreau, P. ^{[1
,2
]}

Denorme, S. ^{[2
]}

Tosti, L. ^{[1
]}

Andrieu, F. ^{[1
]}

Weber, O. ^{[1
]}

Barnola, S. ^{[1
]}

Arvet, C. ^{[2
]}

Campidelli, Y. ^{[2
]}

Haendler, S. ^{[1
]}

Beneyton, R. ^{[2
]}

Perrot, C. ^{[2
]}

de Buttet, C. ^{[1
,2
]}

Gros, P. ^{[2
]}

Pham-Nguyen, L. ^{[2
,3
]}

Leverd, F. ^{[2
]}

Gouraud, P. ^{[2
]}

Abbate, F. ^{[2
]}

Baron, F. ^{[2
]}

Torres, A. ^{[1
]}

Laviron, C. ^{[1
]}

Pinzelli, L. ^{[2
]}

Vetier, J. ^{[2
]}

Borowiak, C. ^{[2
]}

Margain, A. ^{[2
]}

Delprat, D. ^{[4
]}

Boedt, F. ^{[4
]}

Bourdelle, K. ^{[4
]}

Nguyen, B-Y. ^{[4
]}

Faynot, O. ^{[1
]}

Skotnicki, T. ^{[2
]}

机构：

[1] CEA, LETI Minatec, 17 Rue Martyrs, F-38054 Grenoble 9, France

[2] ST Microelect, F-38926 Crolles, France

[3] IMEP, F-38016 Grenoble, France

[4] SOITEC, Pare Technol Fontaines, F-38926 Crolles, France

来源：

2009 PROCEEDINGS OF ESSCIRC | 2009年

关键词：

D O I：

10.1109/ESSDERC.2009.5331588

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we explore for the first time the impact of an Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50mV DIBL reduction by using 10nm BOX thickness for NMOS and PMOS devices at 33nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299 mu m(2) SRAM cell while maintaining an SNM of 296mV @ Vdd 1.1V.

引用

页码：89 / +

页数：2