Energy-Efficient MRAM Access Scheme Using Hybrid Circuits Based on Spin-Torque Sensors

Reducing the energy dissipation for on-chip memory access and the associated data transport is critical for emerging chip multiprocessors (CMP). STT-MRAM is a promising technology for future on-chip memories, owing to its attractive features like non-volatility, zero-leakage and high-density. In an MRAM, read-access and data-transport can dominate the energy-dissipation (owing to negligible leakage power and more frequent read as compared to write operations). We propose the application of nano-scale spin-torque switches for low energy MRAM access. Such spin torque switches can act as fast, compact and ultra-low voltage current-sensors that can be used to perform low-power read operations in MRAM. Such spin-torque sensors (STS) can also facilitate ultra-low voltage, current-mode data transport over global interconnects, thereby reducing the energy dissipation on data buses by more than 99%. Simulation results for 2-level MRAM-cache design using such a STS device shows the possibility of similar to 90% reduction in memory access power as compared to conventional techniques.