High Throughput Architecture for High Performance NoC

被引：7
作者：
Abd El Ghany, Mohamed A. [1 ]
El-Moursy, Magdy A. [2 ,3 ]
Ismail, Mohammed [4 ,5 ]
机构：
[1] German Univ Cairo, Dept Elect Engn, Cairo, Egypt
[2] Mentor Graph Corp, Cairo, Egypt
[3] Elect Res Inst, Cairo, Egypt
[4] Ohio State Univ, Elect Engn Dept, Columbus, OH USA
[5] KTH Royal Inst Technol, RaMSiS Grp, Stockholm, Sweden
来源：
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 | 2009年
关键词：
BFT; NoC; Throughput; Latency;
D O I：
10.1109/ISCAS.2009.5118244
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.
引用
收藏
页码：2241 / 2244
页数：4
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