A Slim Transmission Line Design with Patterned Ground Shields for CMOS mm-Wave Integrated Circuits

An optimized multi-metallization transmission line design with a slim profile and layout simplicity is proposed for CMOS millimeter-wave integrated circuits (ICs). In its quasi-rectangular coaxial structure, the bottom ground-shielding plate adopts a parallel-strip pattern. With the ground-shielding strips laid out perpendicular to the signal-carrying core, the capacitance per unit length of the on-chip transmission line is reduced while the electric field leakage to the substrate is kept to minimum. In a 65-nm CMOS process, the design gives a low insertion loss (less than 1.57 dB/mm) and a low reflection loss (less than -20 dB) at 60 GHz, as verified by 3D electromagnetic simulation. Besides, by simply adopting different strip spacing in the patterned ground shields, the characteristic impedance Z(0) of the transmission line can be adjusted by the IC layout up to 66 Omega or slightly higher. With its layout-adjustable Z(0) and chip-area efficiency (occupying smaller than 17 mu m in width), the transmission line design is potentially versatile for constructing millimeter-wave passive circuits such as Wilkinson power dividers/combiners and impedance matching circuits.