Trends in IC Packaging

被引:0
作者
Beelen-Hendrikx, Caroline [1 ]
机构
[1] NXP Semicond, NL-6534 AE Nijmegen, Netherlands
来源
2009 EUROPEAN MICROELECTRONICS AND PACKAGING CONFERENCE (EMPC 2009), VOLS 1 AND 2 | 2009年
关键词
Cost Reduction; Reliability; Sensors & MEMS; Embedding; 3D Packaging; Memory Integration; Thin Dies;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Drivers for new pack-age development are cost reduction, form factor requirements, reliability, electrical performance and function integration. Cost reduction is realized by improvement of existing packaging plaforms, such as material cost reduction, and changes in processes and design methods, and by introducing new pack-aging platforms. Future low cost packaging platforms will be based on batch processes, large format processing, use of low cost substrates or no substrates at all, and will avoid over specification. Embedded packaging is a new technology that is either based on wafer fob technology or PCB fab technology. Wafer Jab technology based embedded packages give the highest reduction in form factor but are relatively expensive. PCB Jab technology based embedded packages are less expensive but have lower definition. Therefore, they will first be used for low pin count packages. Embedding in motherboards or interposers is a way to reduce package thickness; it is expected to be mainstream for simple, low pin count products. Pack-age reliability requirements are tightened by automotive and lighting businesses, requiring, high temperature, long lifetime and zero delamination. To meet the requirements, interfacial strength and interconnect robustness need to be improved. New functions are realised by silicon based sensors and MEMS, e.g. for automotive, medical, environmental and communication purposes. Pack-aging challenges include wafer treatment, MEMS protection and the realization of die access for fluids and gases to be analyzed. Function integration drives the development of 3D packaging technologies. Ultimate technology is heterogeneous integration by 3DIC. This technology optimizes electrical performance and form factor. For 3DIC ultra-thin dies are stacked by fine pitch flip chip interconnect and silicon through vias. Disadvantage is cost. Therefore, for many applications, stacked die wire-bonded IC packages are still popular. They offer improved bandwidth, power consumption and size, and equal cost compared to separate pack-ages. For 3DIC and also for products such as RFID tags and medical plasters, ultrathin dies are needed. These require dedicated thinning and dicing technologies with use of temporary carriers.
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页码:12 / 19
页数:8
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