Die-Package-PCB Signal Integrity Performance Debug of a High-Speed (25Gbps) Retimer: Simulation to Measurement Correlation

In this paper we detail the signal integrity performance debug of a 130nm BiCMOS high-speed (25Gbps) 4-channel multi-rate retimer device, packaged in a small 7mmx7mm new fine pitch ball grid array (nFBGA), a laminate-based family of chip-scale packaging technology. During the electrolytic plating IC packaging manufacturing process, residual plating tie-bar, i.e. "stubs", can introduce "quarter-wavelength" resonance which can impact signal integrity performance. We discussed here the process of troubleshooting a resonance issue observed during system performance characterization. Key figure of merits for system electrical performance (viz. insertion loss, return loss, crosstalk/isolation, and jitter) are modeled and analyzed. Laboratory measurements are presented that validate the integrity of the system co-design modeling methodology. Good correlation between simulations and laboratory measurements is achieved. Design optimization schemes, to alleviate resonance issues, are implemented and validated with the modeling methodology.