High-Speed and Area-Efficient LUT-Based BCD Multiplier Design

For scientific, research, business and financial purpose multiplication is the rudimentary mathematical operation. Besides, BCD (Binary Coded Decimal)representation is prevailing in the computing and electronic communication for its accuracy and human-readability with ease of conversion. In this paper, an N x M-digit BCD multiplication algorithm is proposed, where the recoding, partial product generation,partial product reduction and BCD conversion steps of the conventional multiplication process are avoided for efficiency. Moreover, BCD multiplier is more effective with a LUT (Look-Up Table)-based design, due to FPGA (Field Programmable Gate Array) technology's enumerable benefits and applications. An area and delay efficient N x M-digit multiplier circuit is demonstrated followed by a 1-Digit LUT-based direct multiplier circuit. The proposed single digit multiplier circuit is 28.57% and 38.32% area and delay efficient respectively than the existing best known single digit multiplier circuit. Moreover, the proposed N x M-digit multiplier circuit is 19.79% and 33.98% efficient in terms of area and delay parameter, respectively for 16 x16 digit multiplication.