A Flexible Real-Time Stereo Vision Architecture for Multiple Data Streams with Runtime Configurable Parameters

被引:0
|
作者
Meng, Zhaoteng [1 ,2 ]
Shu, Lin [1 ,3 ]
Hao, Jie [1 ,3 ]
机构
[1] Chinese Acad Sci, Inst Automat, Beijing, Peoples R China
[2] Univ Chinese Acad Sci, Beijing, Peoples R China
[3] Guangdong Inst Artificial Intelligence & Adv Comp, Guangzhou, Peoples R China
来源
2022 32ND INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, FPL | 2022年
关键词
stereo vision; stereo matching; real-time; reconfigurable architecture; SAD; FPGA; multiple-data-stream; HARDWARE; SYSTEM;
D O I
10.1109/FPL57034.2022.00024
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
It is significant for a stereo vision real-time computing system to flexibly adapt to different parameters of stereo matching without re-customizing hardwares. In this paper, a configurable pipelined hardware architecture based on the sum of absolute differences (SAD) algorithm is proposed. We split the SAD calculation into two parts to accommodate pipelined computing. The architecture can be configured with different resolutions, window sizes, and disparity levels without stopping and restarting. In addition, it can be configured as a multiple-data-stream mode and we have developed a configuration generation algorithm for the mode. The presented architecture is synthesized and implemented on a Xilinx ZCU104 board. The evaluation results demonstrate that the real-time computing of 480P, 720P, and 1080P video streams can be process at 250MHz with the peak computing performance of 480P/784fps at the disparity level of 125. It uses 60% LUTs, 34% registers, and 39% BRAM, producing flexible configurability and superior computing performance than the other similar work.
引用
收藏
页码:86 / 93
页数:8
相关论文
共 50 条
  • [1] Real-time architecture of stereo vision for robot eye
    Kim, YoungSu
    Park, SungChan
    Chen, Chao
    Jeong, Hong
    2006 8TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, VOLS 1-4, 2006, : 561 - +
  • [2] Architecture and implementation of real-time stereo vision with bilateral background subtraction
    Han, Sang-Kyo
    Jeong, Mun-Ho
    Woo, SeongHoon
    You, Bum-Jae
    ADVANCED INTELLIGENT COMPUTING THEORIES AND APPLICATIONS: WITH ASPECTS OF THEORETICAL AND METHODOLOGICAL ISSUES, 2007, 4681 : 906 - +
  • [3] Real-Time Low-Power FPGA Architecture for Stereo Vision
    Puglia, Luca
    Vigliar, Mario
    Raiconi, Giancarlo
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017, 64 (11) : 1307 - 1311
  • [4] A FPGA based Real-time Post-Processing Architecture for Active Stereo Vision
    Choi, Seung-min
    Chang, Jiho
    Hwang, Dae Hwan
    18TH IEEE INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS (ISCE 2014), 2014,
  • [5] Real-Time Stereo Vision Hardware Accelerator: Fusion of SAD and Adaptive Census Algorithm
    Yang, Zhenhao
    Liang, Yong
    Lin, Daoqian
    Li, Jie
    Chen, Zetao
    Li, Xinhai
    IEEE ACCESS, 2024, 12 : 154975 - 154989
  • [6] Post-Processing Algorithms for Real-time Active Stereo Vision
    Choi, Seung-min
    Jeong, Jae-chan
    Hwang, Dae Hwan
    18TH IEEE INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS (ISCE 2014), 2014,
  • [7] Wearable Real-Time Stereo Vision for the Visually Impaired
    Balakrishnan, G.
    Sainarayanan, G.
    Nagarajan, R.
    Yaacob, Sazali
    ENGINEERING LETTERS, 2007, 14 (02)
  • [8] Variant center-symmetric census transform for real-time stereo vision architecture on chip
    Zhao, Chenyuan
    Li, Wenxin
    Zhang, Qingxi
    JOURNAL OF REAL-TIME IMAGE PROCESSING, 2021, 18 (06) : 2073 - 2083
  • [9] Variant center-symmetric census transform for real-time stereo vision architecture on chip
    Chenyuan Zhao
    Wenxin Li
    Qingxi Zhang
    Journal of Real-Time Image Processing, 2021, 18 : 2073 - 2083
  • [10] Real-time obstacle detection by stereo vision and ultrasonic data fusion
    Gholami, Farshad
    Khanmirza, Esmaeel
    Riahi, Mohammad
    MEASUREMENT, 2022, 190