共 6 条
[1]
CRANINCKX J, 1996, IEEE J SOLID-ST CIRC, V31, P980
[5]
10 GHz, 20mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a .18μm digital CMOS process
[J].
2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS,
2003,
:181-184
[6]
SHU KL, 1998, LOW POW EL DES 1998, P59