An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET

被引：38
作者：
Kaur, Harsupreet
Kabra, Sneha
Haldar, Subhasis
Gupta, R. S.
机构：
[1] Univ Delhi, Dept Elect Sci, Semicond Device Res Lab, New Delhi 110021, India
[2] Motilal Nehru Coll, Dept Phys, New Delhi 110021, India
来源：
MICROELECTRONICS JOURNAL | 2007年 / 38卷 / 03期
关键词：
device modeling; surrounding gate MOSFET; graded channel; drain current enhancement; reduced drain conductance; improved breakdown voltage;
D O I：
10.1016/j.mejo.2007.01.003
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In the present paper, a comprehensive drain current model incorporating various effects such as drain-induced barrier lowering (DIBL), channel length modulation and impact ionization has been developed for graded channel cylindrical/surrounding gate MOSFET (GC CGT/SGT) and the expressions for transconductance and drain conductance have been obtained. It is shown that GC design leads to drain current enhancement, reduced output conductance and improved breakdown voltage. The effectiveness of GC design was examined by comparing uniformly doped (UD) devices with GC devices of various L-1/L-2 ratios and doping concentrations and it was found that GC devices offer superior characteristics as compared to the UD devices. The results so obtained have been compared with those obtained from 3D device simulator ATLAS and are found to be in good agreement. (C) 2007 Elsevier Ltd. All rights reserved.
引用
收藏
页码：352 / 359
页数：8
相关论文
共 22 条
[1]   PCIM - A PHYSICALLY-BASED CONTINUOUS SHORT-CHANNEL IGFET MODEL FOR CIRCUIT SIMULATION [J].
ARORA, ND ;
RIOS, R ;
HUANG, CL ;
RAOL, K .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (06) :988-997
[2]   Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's [J].
Auth, CP ;
Plummer, JD .
IEEE ELECTRON DEVICE LETTERS, 1997, 18 (02) :74-76
[3]   Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping [J].
Chen, XD ;
Ouyang, QC ;
Wang, G ;
Banerjee, SK .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (11) :1962-1968
[4]   AN ANALYTICAL DRAIN CURRENT MODEL FOR SHORT-CHANNEL FULLY-DEPLETED ULTRATHIN SILICON-ON-INSULATOR NMOS DEVICES [J].
CHEN, YG ;
KUO, JB ;
YU, Z ;
DUTTON, RW .
SOLID-STATE ELECTRONICS, 1995, 38 (12) :2051-2057
[5]   An asymmetric channel SOI nMOSFET for improving DC and microwave characteristics [J].
Dehan, M ;
Raskin, JP .
SOLID-STATE ELECTRONICS, 2002, 46 (07) :1005-1011
[6]  
Endoh T, 1997, IEICE T ELECTRON, VE80C, P911
[7]   Explicit continuous model for long-channel undoped surrounding gate MOSFETs [J].
Iñíguez, B ;
Jiménez, D ;
Roig, J ;
Hamid, HA ;
Marsal, LF ;
Pallarès, J .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (08) :1868-1873
[8]  
KAUR H, IN PRESS SOLID STATE
[9]   Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications [J].
Kranti, A ;
Chung, TM ;
Flandre, D ;
Raskin, JP .
SOLID-STATE ELECTRONICS, 2004, 48 (06) :947-959
[10]   Analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET [J].
Kranti, A ;
Haldar, S ;
Gupta, RS .
MICROELECTRONIC ENGINEERING, 2001, 56 (3-4) :241-259
123