SIP, or System in Package, is a fairly old concept that is enjoying rebirth in a new body, literally. On the scene over the years as a means to create a tightly coupled high performance system using bare chips attached in a single package, the new embodiment of SIP is targeting handheld computing and communication products which require space minimization. For SIP to be successful requires reaching toward new assembly technologies to enable die thinning and stacking. Stacking the multiple chips needed for the system helps to minimize x-y package dimensions, while thinning minimizes total height, especially when stacking many chips. The challenges involve not only those of chip assembly, but also of insuring proper integration of silicon and package which need to bridge across chip design and fabrication, package design and construction, chip assembly and test. This paper will provide an overview of several SIP approaches, describe the required assembly technologies, the key silicon-package integration challenges, and how these are being brought together to enable increasing performance and function in ever decreasing space.
