Characterization and Compact Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures

被引:154
作者
Incandela, Rosario M. [1 ,2 ,3 ]
Song, Lin [4 ,9 ]
Homulle, Harald [1 ,2 ,3 ]
Charbon, Edoardo [3 ,5 ,6 ]
Vladimirescu, Andrei [7 ,8 ]
Sebastiano, Fabio [1 ,2 ,9 ]
机构
[1] Delft Univ Technol, Dept Quantum & Comp Engn, NL-2628 Delft, Netherlands
[2] QuTech, NL-2628 Delft, Netherlands
[3] Kavli Inst Nanosci, NL-2628 Delft, Netherlands
[4] Analog Devices Inc, Beijing 100192, Peoples R China
[5] Ecole Polytech Fed Lausanne, Adv Quantum Architectures Lab, CH-1015 Lausanne, Switzerland
[6] Intel Corp, Hillsboro, OR 97124 USA
[7] Univ Calif Berkeley, Berkeley Wireless Res Ctr, Berkeley, CA 94708 USA
[8] Inst Super Elect Paris, Micronano Elect & Radio Commun, F-75006 Paris, France
[9] Delft Univ Technol, Dept Microelect, NL-2628 Delft, Netherlands
来源
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | 2018年 / 6卷 / 01期
关键词
Cryogenic electronics; CMOS; cryogenic; cryo-CMOS; characterization; modeling; kink; 4; K; LNA; OXIDE-SEMICONDUCTOR TRANSISTORS; THRESHOLD VOLTAGE; MOS-TRANSISTORS; LIQUID-NITROGEN; BEHAVIOR; NOISE; KINK; HYSTERESIS; INTERFACE; FREQUENCY;
D O I
10.1109/JEDS.2018.2821763
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-mu m and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device dc characteristics, the accuracy and validity of the compact models are demonstrated by comparing time- and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier, with the measurements at 4 K.
引用
收藏
页码:996 / 1006
页数:11
相关论文
共 52 条
  • [1] Compact and Distributed Modeling of Cryogenic Bulk MOSFET Operation
    Akturk, A.
    Holloway, M.
    Potbhare, S.
    Gundlach, D.
    Li, B.
    Goldsman, N.
    Peckerar, M.
    Cheung, K. P.
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (06) : 1334 - 1342
  • [2] Akturk A., 2009, 2009 INT C SIM SEM P, P1, DOI DOI 10.1109/SISPAD.2009.5290227
  • [3] Cryogenic transimpedance amplifier for micromechanical capacitive sensors
    Antonio, D.
    Pastoriza, H.
    Julian, P.
    Mandoles, P.
    [J]. REVIEW OF SCIENTIFIC INSTRUMENTS, 2008, 79 (08)
  • [4] BRIEF REVIEW OF THE MOS DEVICE PHYSICS FOR LOW-TEMPERATURE ELECTRONICS
    BALESTRA, F
    GHIBAUDO, G
    [J]. SOLID-STATE ELECTRONICS, 1994, 37 (12) : 1967 - 1975
  • [5] INFLUENCE OF SUBSTRATE FREEZE-OUT ON THE CHARACTERISTICS OF MOS-TRANSISTORS AT VERY LOW-TEMPERATURES
    BALESTRA, F
    AUDAIRE, L
    LUCAS, C
    [J]. SOLID-STATE ELECTRONICS, 1987, 30 (03) : 321 - 327
  • [6] Cryogenic Characterization of 28 nm Bulk CMOS Technology for Quantum Computing
    Beckers, Arnout
    Jazaeri, Farzan
    Ruffino, Andrea
    Bruschini, Claudio
    Baschirotto, Andrea
    Enz, Christian
    [J]. 2017 47TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2017, : 62 - 65
  • [7] Wide-band CMOS low-noise amplifier exploiting thermal noise canceling
    Bruccoleri, F
    Klumperink, EAM
    Nauta, B
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (02) : 275 - 282
  • [8] CMOS reliability issues for emerging cryogenic Lunar electronics applications
    Chen, Tianbing
    Zhu, Chendong
    Najafizadeh, Laleh
    Jun, Bongim
    Ahmed, Adnan
    Diestelhorst, Ryan
    Espinel, Gustavo
    Cressler, John D.
    [J]. SOLID-STATE ELECTRONICS, 2006, 50 (06) : 959 - 963
  • [9] Temperature dependences of threshold voltage and drain-induced barrier lowering in 60 nm gate length MOS transistors
    Chen, Zehua
    Wong, Hei
    Han, Yan
    Dong, Shurong
    Yang, B. L.
    [J]. MICROELECTRONICS RELIABILITY, 2014, 54 (6-7) : 1109 - 1114
  • [10] Coskun A, 2014, IEEE INT SYMP CIRC S, P2001, DOI 10.1109/ISCAS.2014.6865556