Efficient design error correction of digital circuits

Equivalence checking of two circuits is performed at several stages in the design cycle of hardware designs and various commercial equivalence checkers, mostly based on Boolean logic, are already in the market. Design Error Diagnosis and Correction (DEDC) methods come into play when equivalence checking has proven two circuits to be different in many cases, DEDC methods can locate and correct design errors fully automatically. In this paper,ve present an efficient symbolic method for automatic error correction of both combinational and synchronous sequential circuits. We first address the problem of receiving combinational circuits and then show how the problem of rectifying sequential circuits can be reduced to a combinational problem without unrolling the combinational logic parts. In addition, rye introduce several optimizations to our algorithm. All optimizations are safe, meaning that they neither affect the number of computed solutions nor do they decrease the quality of results. Our experimental results show that the discussed optimization strategies call make the rectification procedure 2 to 16 times faster than the unoptimized algorithm.