A FPGA Verification of Improvement Edge Detection using Separation and Buffer Line

被引：0

作者：

Peng, Tao ^{[1
]}

Thathupara ^{[1
]}

Erdenetuya ^{[1
]}

Jang, Young-Min ^{[1
]}

Cho, Sang-Bock ^{[1
]}

机构：

[1] Univ Ulsan, Sch Elect Engn, Ulsan, South Korea

来源：

2020 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC) | 2020年

关键词：

image processing; edge detection; buffer line; FPGA;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper investigates the performance of an improved edge detection algorithm on an FPGA platform. The algorithm has three blocks: gray scale and Gaussian filter, separation and buffer line, Prewitt filter. Separation and buffer line method are needed to improve edge detection speed. Therefore, when converting to frames per second, the speed is improved to 183frames/s, which is faster than conventional method. A proposed algorithm was implemented using Matlab program and it is verified through a RTL-level simulation of ISE14.3.

引用

页数：3

共 7 条

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