Switching activity minimization in combinational logic design

被引：0

作者：

Menon, RV ^{[1
]}

Chennupati, S ^{[1
]}

Samala, NK ^{[1
]}

Radhakrishnan, D ^{[1
]}

Izadi, B ^{[1
]}

机构：

[1] SUNY Albany, Dept Elect & Comp Engn, New Paltz, NY 12561 USA

来源：

ESA'04 & VLSI'04, PROCEEDINGS | 2004年

关键词：

switching activity; multi-level implementation; implicant; implicate; low-power; CMOS circuit;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal optimal solution obtained from k-map to reduce its switching activity. More than 10% reduction in switching activity has been observed using our method. The final solution gives a good trade off between cost and power consumption.

引用

页码：47 / 53

页数：7

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