Synchronization design of a coupled phase-locked loop

被引：20

作者：

Buckwalter, JF ^{[1
]}

Heath, TH

York, RA

机构：

[1] CALTECH, Dept Elect Engn, Pasadena, CA 91125 USA

[2] Univ Calif Santa Barbara, Dept Elect & Comp Engn, Santa Barbara, CA 93106 USA

[3] Georgia Tech Res Inst, Sensors & Electromagnet Applicat Lab Div, Smyrna, GA USA

来源：

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES | 2003年 / 51卷 / 03期

关键词：

coupled phase-locked loop (CPLL); hold-in range; pull-in range; time delay;

D O I：

10.1109/TMTT.2003.808701

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Coupled phase-locked loops (CPLLs) are introduced as novel circuits for phased-array antennas. Successful implementation relies on characterizing the synchronization behavior of CPLL circuits over a broad range of circuit parameters. Considering inherent time delay in the phase-locked loop demonstrates the degradation in the pull-in and hold-in ranges, as well as circuit instabilities, suggesting circuit parameter limits in a phased-array design. We compare the theoretical limits, in the form of analytic equations and numerical simulations, with measurements of the pull-in and hold-in processes of a 1.5-GHz prototype CPLL.

引用

页码：952 / 960

页数：9

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