A Novel Energy-Efficient Ternary Successor and Predecessor Using CNTFET

被引:10
作者
Mastoori, Maryam Sadat [1 ]
Razaghian, Farhad [1 ]
机构
[1] Islamic Azad Univ, South Tehran Branch, Dept Elect Engn, Tehran, Iran
关键词
Carbon nanotube field-effect transistor (CNTFET); Ternary logic; Successor; Predecessor; Multiple-valued logic (MVL) design; TRANSISTORS INCLUDING NONIDEALITIES; COMPACT SPICE MODEL; DESIGN; CIRCUITS; NANOTECHNOLOGY; ELECTRONICS; DEVICE;
D O I
10.1007/s00034-015-0084-7
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a novel design for a ternary successor and predecessor using carbon nanotube field-effect transistors (CNTFETs). The chirality of the CNTFETs is utilized for threshold voltage control. The proposed designs are simulated and examined, using Synopsys HSPICE with Standard 32 nm CNTFET technology in various situations. Simulation results demonstrate the correct and high-performance operation of the proposed circuits even in the presence of process variations. It is shown that the proposed ternary circuits achieve a significant saving in energy consumption (95.18 % for successor and 91 % for predecessor) compared with previously presented designs.
引用
收藏
页码:875 / 895
页数:21
相关论文
共 19 条
[1]   Carbon nanotubes for high-performance electronics - Progress and prospect [J].
Appenzeller, J. .
PROCEEDINGS OF THE IEEE, 2008, 96 (02) :201-211
[2]   LOW POWER DISSIPATION MOS TERNARY LOGIC FAMILY. [J].
Balla, Prabhakara C. ;
Antoniou, Andreas .
IEEE Journal of Solid-State Circuits, 1984, SC-19 (05) :739-749
[3]  
Cho G., 2009, I2MTC 2009 IEEE INST
[4]   A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - Part II: Full device model and circuit performance benchmarking [J].
Deng, Jie ;
Wong, H. -S. Philip .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (12) :3195-3205
[5]   A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - Part I: Model of the intrinsic channel region [J].
Deng, Jie ;
Wong, H. -S. Philip .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (12) :3186-3194
[6]   On modelling and characterization of single electron transistor [J].
El-Seoud, A. K. Abu ;
El-Banna, M. ;
Hakim, M. A. .
INTERNATIONAL JOURNAL OF ELECTRONICS, 2007, 94 (6-8) :573-585
[7]   Efficient Carbon Nanotube Galois Field Circuit Design [J].
Keshavarziana, Peiman ;
Navi, Keivan .
IEICE ELECTRONICS EXPRESS, 2009, 6 (09) :546-552
[8]  
Kim Y.-B., 2009, P IEEE INT MIDW S CI
[9]  
Lin S., 2009, P IEEE INT MIDW S CI
[10]   CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits [J].
Lin, Sheng ;
Kim, Yong-Bin ;
Lombardi, Fabrizio .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2011, 10 (02) :217-225