Implementing interval type-2 fuzzy processors

被引：56

作者：

Melgarejo, Miguel ^{[2
]}

Pena-Reyes, Carlos A.

机构：

[1] Novartis, Basel, Switzerland

[2] Univ Distrital FJC, Bogota, Colombia

来源：

IEEE COMPUTATIONAL INTELLIGENCE MAGAZINE | 2007年 / 2卷 / 01期

关键词：

D O I：

10.1109/MCI.2007.357195

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The implementation of interval type-2 fuzzy processors (IT2-FP), which takes advantage of the parallelism in hardware realizations, is presented. It details particular considerations for the design of the different components of the architecture. The model uses four stages to compute an entire type-2 fuzzy inference, comprising singleton fuzzification, inference engine, approximated type-reduction (TR), and defuzzification. There are four stages in the architecture of the processor, comprising a fuzzification array, a rule unit array, a type-reduction circuit and an additional control unit. The control unit of the processor is a simple circuit that is in charge of synchronizing the operations and the data flow among the others parts of the processor. Several design options have been presented for implementing the different components of the processor.

引用

页码：63 / 71

页数：9

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